1. Field of Invention
The present invention relates to a semiconductor device and the fabricating method thereof, and more particularly to a chip package and the fabricating method thereof.
2. Description of Related Art
In the semiconductor industry, the manufacture of integrated circuits (IC) is mainly divided into three stages, namely IC design, IC process, and IC package.
During the fabrication of ICs, a chip is obtained through steps of wafer fabrication, IC forming, and wafer dicing. The wafer has an active surface which generally refers to the surface of the wafer with active devices. After the IC on the wafer is finished, a plurality of chip pads is disposed on the active surface of the wafer, such that the chip formed finally through wafer dicing is electrically connected to a carrier through the chip pads. The carrier is, for example, a leadframe or a package substrate. The chip is connected to the carrier by means of wire bonding or flip chip bonding, so as to make the chip pads of the chip electrically connected to the contact of the carrier. Thus, a chip package is formed.
As for the flip chip bonding technology, usually after the chip pads are formed on the active surface of the wafer, a bump is fabricated on each of the chip pads for use in electrically connecting the chip to the external package substrate. Since the bumps are usually arranged on the active surface of the chip in a plane array, the flip chip bonding technology is suitable for chip packages of high contact number and high contact density, for example, a flip chip/ball grid array package commonly used in the semiconductor package industry. Besides, compared with the wire bonding technology, the flip chip bonding technology may enhance the electrical performance of the chip package because the bumps provide a short transmission path between the chip and the carrier.
Referring to FIG. 1, it is a sectional view of a conventional chip package. A conventional chip package 100 includes a chip 110, a package substrate 120, a plurality of bumps 130, and an interface metal layer 140. The chip 110 has a plurality of chip pads 112 disposed on a surface 114 of the chip 110. The package substrate 120 has a plurality of first substrate pads 122, a plurality of second substrate pads 124, and a surface bonding layer 126. The first substrate pads 122 and the second substrate pads 124 are disposed on a surface 128 of the package substrate 120. The surface bonding layer 126 (the material thereof is Sn) is disposed on the first substrate pads 122 and the second substrate pads 124, and the layer 126 also completely covers the first substrate pads 122 and the second substrate pads 124.
The bumps 130 are respectively disposed between the chip pads 112 and the surface bonding layer 126. The interface metal layer 140 is disposed between the bumps 130 and the surface bonding layer 126. The chip 110 is electrically connected to the package substrate 120 through the bumps 130. Additionally, each first substrate pad 122 is electrically connected to one of the bumps 130, and each second substrate pad 124 is electrically connected to two or more of the bumps 130. It should be noted that the surface bonding layer 126 is used to provide a better bonding between the bumps 130 and the correspondingly-connected first substrate pads 122 or second substrate pads 124.
In general, the surface area of the surface bonding layer 126 formed on the second substrate pads 124 is much larger than the total contact surface area of the connected bumps 130, while the surface area of the surface bonding layer 126 formed on the first substrate pads 122 is slightly larger than the contact surface area of the connected bumps 130.
The conventional chip package 100 is formed by a thermal compression bonding process. In particular, after the bumps 130 are respectively formed on the chip pads 112 in advance, and the surface bonding layer 126 is formed on the first substrate pads 122 and the second substrate pads 124, each of the bumps 130 is then pressed onto one of the first substrate pads 122 or of the second substrate pads 124 by means of high-temperature compression. Each of the bumps 130 chemically reacts with the surface bonding layer 126 to form the interface metal layer 140, so that the chip 110 is electrically connected to the package substrate 120.
During the thermal compression bonding process, as the surface area of the surface bonding layer 126 formed on the first substrate pads 122 is slightly larger than the contact surface area of the connected bumps 130, the contact surface area may be quickly increased to be equal to the surface area of the surface bonding layer 126 formed on the first substrate pads 122. As such, the material of the surface bonding layer 126 may be completely used to connect the bumps 130.
However, as for the second substrate pads 124, the overall contact surface area of the bumps 130 may not be increased to be equal to the surface area of the surface bonding layer 126 formed on the second substrate pads 124, so parts of the surface bonding layer 126 respectively disposed on the second substrate pads 124 in a melting state rises along the side of the bumps 130 toward the chip 110 and further contaminates the chip 110.